This invention relates to the field of high frequency Phase Locked Loops (`PLL`s) and, in particular, to digital or quasi-digital PLLs.
Many attempts to fabricate very high frequency (100 MGz+) PLLs as integrated circuits (`IC`s) have been made. Although some high frequency PLLs have been successfully fabricated as ICs, traditional analog PLLs are difficult to fabricate as ICs as the PLL requires many analog circuit elements and interactive resistor-capacitor (`RC`) time-constants. Due to process variations, these analog IC PLLs tend to have a great deal of variation in their performance specifications. Additionally, conventional digital PLLs require a clock frequency many times higher than the PLLs' operating frequency in order to achieve acceptable phase resolutions. This requirement for a high frequency block, which may need to operate at frequencies higher than 1 GHz, has limited the use of digital PLLs in very high speed applications.
A new method and apparatus for implementing a quasi-digital high frequency PLL is shown in FIG. 1. Digital PLL 10 comprises, in this embodiment, phase detector 12, signed phase-to-frequency (`P-to-F`) converter 14, 3-Phase ring oscillator 16 and Frequency-Controlled Oscillator (`FCO`) 18. The use of FCO 18 and P-to-F converter 14 allows the use of a clock frequency which is no higher than the generating frequency of the PLL to achieve acceptable phase resolution.
The technique and apparatus shown in FIG. 1 requires signed P-to-F converter 14 to convert the phase error information generated by phase detector 12, which is in the form of UP, DOWN and HOLD, to multiphase analog waveforms to drive FCO 18. The output frequency of P-to-F converter 14 determines the locking range of PLL 10 (f.sub.in =f.sub.PLL-CLK=f.sub.Local CLK .+-.f.sub.m, where f.sub.m is the output frequency of the P-to-F converter). The phase error direction, either plus or minus, is represented by the phase relationship, either leading or lagging, of the multi-phase outputs from P-to-F converter 14 (Phases 1, 2, and 3), which FCO 18 interprets as either an increase in the operating frequency or a decrease in the operating frequency.
Known methods to create a digital multi-phase P-to-F converter was complicated state machines to perform the necessary signal conversion and waveform synthesis, followed by digital-to-analog converters and anti-aliasing filters. This approach is not cost-effective and requires the fabrication of many precision analog circuits, which cannot be done with sufficient consistency. A digital P-to-F converter of simpler design would be a significant advance on known digital P-to-F converter, especially where high frequency operation is needed.